1. Field of the Invention
The present invention relates to a method for fabricating a CMOS device using an silicon-on-insulator(SOI) substrate, and more particularly to a method for fabricating CMOS device capable of improving mobility of electron and hole.
2. Description of the Related Art
Due to the fast development in semiconductor device industry, a semiconductor device using the SOI substrate instead of a silicon substrate made of bulk silicon, has been proposed. According to this SOI device, adjoining devices are completely isolated from each other and a reduction of the junction capacitance can be obtained, therefore a low power and high speed device can be manufactured.
FIG. 1 is a cross-sectional view showing a conventional SOI substrate provided with a field oxide film. As shown in the drawing, the SOI substrate 10 has a stacking structure comprising a base layer 1 as a supporting means and a semiconductor layer 3 in which a device is to be formed later, and a buried oxide layer 2 being sandwiched between the base layer 1 and the semiconductor layer 3. This SOI substrate 10 is generally manufactured by the SIMOX(separation by implanted oxygen) method implanting oxygen ions and the bonding method that two silicon substrates are bonded each other.
The characteristic of the device formed on the SOI substrate depends on the thickness of semiconductor layer. For instance, the characteristic of the device is improved when the thickness of semiconductor layer 3 is uniform. The thickness of semiconductor layer 3 is preferable to be set below 100 nm.
On the other hand, as shown in the drawing, in the SOI substrate 10 provided with an isolation layer, i.e. the field oxide film 4 formed by the LOCOS process, the field oxide film 4 is formed to be contacted with the buried oxide layer 2, therefore an external stress is applied to the semiconductor layer 3 during the formation of field oxide film 4. However, when a CMOS device comprising NMOS and PMOS is formed on the semiconductor layer 3, it is difficult to expect an enhanced CMOS device.
In detail, it is well known that when a CMOS comprising NMOS and PMOS is formed in the semiconductor layer being affected by the external stress, the electron mobility in the NMOS is decreased while the hole mobility in the PMOS is increased. For example, the more the stress within the semiconductor layer, the smaller the electron mobility, and the more the compressive stress within the semiconductor layer, the more the hole mobility.
Further, it is disclosed in the "Silicon-On-Insulator technology and devices VIII" edited by S. Cristoloveanu, pp. 335 that the hole mobility in the semiconductor layer of the SOI substrate, is larger than the hole mobility in the bulk silicon when the compressive stress is applied to the semiconductor layer.
Accordingly, the CMOS device with high speed and low power consumption should have a desired degree of hole mobility in the PMOS and electron mobility in the NMOS device. However, when the CMOS device is formed on the SOI substrate by the conventional method, both mobilities are not improve at the same time, therefore it is difficult to obtain those properties applicable to the manufacturing process of the device with high speed and low power consumption.